Field of the Invention
The invention relates to a memory circuit having a memory cell array to be tested. The invention furthermore relates to a method for reading out data from a memory circuit, in particular, while testing the memory circuit.
Dynamic semiconductor memories have a memory cell array in which memory cells are addressable via word lines and bit lines. The memory cells essentially include a storage capacitor, which is connected to the respective bit line in a switchable manner through the activation of a word line, so that the charge of the capacitor is added to the corresponding bit line. The bit lines are organized in pairs. The activation of a word line results in only one storage capacitor being applied to one of the two lines of the bit line pair. This results in a charge difference between the bit lines of the bit line pair, which is amplified using a primary sense amplifier and made available to a secondary sense amplifier. In this case, a plurality of primary sense amplifiers form a group and are connected to the secondary sense amplifier in each case via a switching device. Depending on the read-out address present, one of the switching devices is activated in order to apply the datum read out from the respective primary sense amplifier to the secondary sense amplifier. The datum present at the secondary sense amplifier can then be accepted.
Semiconductor dynamic random access memories (DRAMs) have to be comprehensively tested in accordance with predetermined specifications after their production. In particular, a test is performed in accordance with a predetermined specification to check the time period between the application of the word line activation signal (the RAS signal) and the application of the bit line activation signal (the CAS signal), which connects the primary sense amplifier to the secondary sense amplifier. The RAS signal brings about activation of the respectively addressed word line, and the CAS signal effects the acceptance of the datum to be read out from the respective primary sense amplifier into the secondary sense amplifier.
The CAS signal serves for accepting the signal present at the input of the secondary sense amplifier. The timing TRCD (Timing RAS-CAS Delay) between the activation of the word line, after which the charge difference on the bit line pairs is amplified by the primary sense amplifiers, and the application of the amplified signal to the input of the secondary sense amplifier is critical and must correspond to the specification.
In order to test this timing parameter TRCD, it is necessary to check every possible address successively. In other words, the memory cells of the cell array have to be addressed with a burst length of “1” and a fast_X addressing pattern. This is a very slow way for testing the memory cell array with regard to the timing parameter TRCD. Depending on the specification of the DRAM memory to be tested, seven clock cycles are thus required for an address.
This has the disadvantage that all the addresses of the memory cell array have to be tested successively when testing the TRCD timing, with the result that a considerable test time is required for testing the specification of this parameter.